The invention relates to a method of fabricating an integrated circuit in a microelectronic device. More particularly, the present invention relates to a method of forming smaller lithography patterns on substrates by using phase shifting masks.
The fabrication of integrated circuits and semiconductor devices requires the application of a lithography process to define a pattern on a substrate. A photosensitive layer on a substrate is patternwise exposed with radiation that passes through a mask having opaque and transparent regions. A commonly used mask called a binary mask is comprised of an opaque material such as chrome or chromium on a transparent substrate which is typically quartz. The electric field or aerial image that exits from the mask during an exposure has a high intensity corresponding to light passing through transparent regions and a low intensity where light has been blocked by opaque regions. The aerial image is projected onto a photosensitive film called a photoresist to form exposed regions and unexposed regions. A small amount of radiation does reach xe2x80x9cunexposedxe2x80x9d regions, especially near borders with exposed regions because of diffracted light. This condition limits the minimum size of the features that can be formed or resolved in the photoresist pattern. Since there is a constant demand for decreasing feature size in order to build faster circuits or for a higher density of circuits per unit area, numerous resolution enhancement techniques have been developed during the past several years.
The minimum feature size that can be printed for a given process is defined as R=kxcex/NA where R is the minimum resolution, k is a constant for the process, xcex is the exposing wavelength, and NA is the numerical aperture of the projection optics in the exposure tool. A combination of lower k and lower xcex coupled with a higher NA has enabled a steady reduction in technology nodes in recent years from over 250 nm to 180 nm, 130 nm, and now to 100 nm. Traditionally, k is reduced by enhancements to the mask or lithographic process such as attenuated masks, off-axis illumination (OAI), optical proximity correction (OPC), scattering bars (SB) and high contrast photoresists.
The most popular exposure tools have been g-line (436 nm) and i-line (365 nm) steppers and scanners but Deep UV (248 nm) tools have been implemented to achieve resolution in the 130 nm to 250 nm range. Currently, 193 nm exposure tools are being accepted as the primary path to the 100 nm node. With each step in xcex reduction, the NA has been maximized to be in a range of about 0.7 to 0.85. If all the advances in k, xcex, and NA are combined, the minimum feature size that can be achieved is about half wavelength. In other words, for the current technology based on 193 nm exposure tools, the smallest feature that can be reliably produced in manufacturing is about 90 to 100 nm. There is a need to push the imaging capability toward quarter wavelength with new optical enhancements since the time gap between each technology node is becoming shorter and exceeds the ability of tool manufacturers to match the pace with xcex and NA improvements. This is especially true for gate electrodes in transistors where the feature size is already sub-100 nm and is rapidly decreasing.
Attenuated phase shift masks have been widely introduced into manufacturing processes because they can enable a smaller resolution feature to be printed with a larger process window than with binary masks. One example is found in U.S. Pat. No. 6,210,841 in which an attenuated mask is formed by adding an attenuator material such as MoSiOxNy to portions of the substrate. The thickness of the MoSiOxNy is adjusted so that the phase of the light is shifted by 180xc2x0 in regions where radiation passes through the attenuator. Scattering bars are also used to improve the resolution of the process to 130 nm.
A photoresist process is also characterized by its process latitude. That is the combination of focus and exposure dose settings that will generate a photoresist feature within a given linewidth or space width tolerance which is usually within xc2x110% of a targeted value. A focus latitude or depth of focus (DOF) of at least 0.4 microns and preferably near 1 micron or larger is desirable for an acceptable manufacturing process. At the same time, the dose latitude or acceptable range of exposure doses should be at least 10% (xc2x15% about a target dose) and preferably 15% or greater. As an example, a gate feature size of 180 nm that is printed at a dose of 20 mJ/cm2 and with a process having a DOF of 1 um and a dose latitude of 20% means that a feature sizes between 162 nm and 198 nm can be printed if the exposure dose stays within a range of 18 mJ/cm2 to 22 mJ/cm2 and the focal plane does not shift from best focus by more than 0.5 micron (xcexcm) in either direction (toward plane of substrate or away from substrate). A phase shifted mask can help to increase process latitude besides improving resolution. This is valuable because expensive rework involving stripping the resist layer, recoating and re-exposing when linewidth is out of specification can be reduced which leads to a lower cost device.
An alternating phase shift (alt-PSM) approach first proposed by Levenson in 1988 appears to be the best method of achieving a quarter wavelength resolution. In the case of an alt-PSM with a single trench etched into the substrate as illustrated in FIG. 1a, exposing radiation 2 passes through two transparent regions with thicknesses t1 and t1+t2 on opposite sides of an opaque region 4. The amount of quartz 6 that has been removed in the second transparent region to form trench 7 is thickness t2 that has been determined according to an equation (nxe2x88x921)xc3x97(t2)=xc2xdxcex where n is the refractive index of the quartz 6 and xcex is the exposing wavelength. The result is that the phase of light exiting region with thickness t1 (through aperture B) is 180xc2x0 out of phase with the light exiting the adjacent region with thickness t1+t2 (through aperture A). The phase width is shown as the distance PW. This relationship forms a higher contrast aerial image that exposes the photosensitive film on the substrate and allows smaller feature sizes to be printed with an alternating mask 3 than with a binary mask which has a uniform thickness of quartz and light of only one phase exiting apertures of the mask.
An alt-PSM 3 with a dual trench is shown in FIG. 1b. Trench 8 with a depth t3 and trench 9 with a depth t4 are etched into quartz 6. Distances t3 and t4 are adjusted so that radiation 2 that passes through alt-PSM 3 exits aperture C with a phase xcex8xc2x0 and exits aperture D with a phase (180+xcex8)xc2x0. The distance (t2, t3, or t4) that a trench is etched into a mask substrate will hereafter be referred to as a phase depth.
However, fabrication of alt-PSMs has been difficult in terms of automatic phase assignment, phase inspection and repair, and cycle time which increases cost beyond what many IC manufacturers can afford. Alt-PSM has a phase conflict problem because it creates dark resist (unexposed positive tone photoresist) at all areas corresponding to a 0xc2x0 to 180xc2x0 transition in the mask. Meanwhile, automatic phase assignment and alt-PSM design rule for an IC layout are very crucial for real applications. Spence (U.S. Pat. No. 5,573,890) and Wang (U.S. Pat. Nos. 5,858,580 and 6,228,539) reveal double exposure alt-PSM to overcome these concerns. Spence uses an alt-PSM and a structure mask in order to achieve a new gate length and remove unwanted dark lines formed by the phase shift method. However, this solution does not avoid the difficulty of making the mask. It also does not address polysilicon interconnect lines that must shrink in dimension simultaneously with a smaller gate size in order to realize the full benefit of smaller gates. Wang uses a dark field phase shifting mask for shrinking gate length and a structure mask to define polysilicon interconnects as well as protecting the shrunken gate. There is no alt-PSM rule checking to resolve phase conflicts and the structure mask is binary with a relaxed design rule that prohibits features near quarter wavelength from being printed.
Another alt-PSM technique is described in U.S. Pat. No. 5,994,002 and is primarily concerned with mask corrections to control an optical proximity effect where lines of equal size on the mask are separated by different space widths. Uncorrected masks tend to print isolated lines larger than dense lines in resist films. While the method deals with optical proximity effects, it does not mention correcting for lens aberrations or adjusting two different features on a mask which are printed simultaneously such as gate lines and polysilicon interconnects.
Still another alt-PSM method described in U.S. Pat. No. 5,882,827 combines alt-PSM and attenuated PSM features on the same mask to overcome alignment concerns. The mask appears difficult to produce because in some cases, the attenuated shifter material is overlaid on alt-PSM regions where the transparent quartz has been removed to adjust its thickness relative to the non-shifted transparent regions. This arrangement would be difficult to inspect and repair and therefore costly to make.
For the 100 nm technology node that is currently being implemented in manufacturing, gate lengths as small as 60 or 70 nm are being produced and there is no method with current lithography techniques to achieve this dimension. Typically, 100 nm gate features are printed in resist and then trimmed by a plasma etch to achieve a smaller size. This method requires an extra step of etching which can be costly and difficult to control if two or more feature sizes are trimmed at the same time. Therefore, it is desirable to have a lithography technique that is able to print features in photoresist that are about one quarter the size of the exposing wavelength. The method should provide an acceptable process window and be compatible with a manufacturing process flow. A logical layout management flow should be provided so that an appropriate mask or masks can be built.
One objective of the present invention is to provide a method for forming a feature in a photoresist layer that has a smaller dimension than can be produced by conventional resolution enhancement techniques. This is especially true for gate lengths.
A further objective of the present invention is to provide a method of shrinking two different features simultaneously such as a gate length and a polysilicon interconnect in an integrated circuit.
A still further objective of the present invention is to provide a data processing flow for defining a layer in an integrated circuit. The data enables an improved alt-PSM mask to be built in addition to a trim mask which together can be used to print shrunken gate and interconnect feature sizes.
A still further objective of the present invention is to provide a system for producing phase shifting layout data which can handle alt-PSM design rules, optical proximity corrections (OPC), scattering bar rules and gate blocking area generation for tritone attenuated PSM mask making.
These objectives are achieved through the design of an alt-PSM with full size scattering bars (FSSB) and an attenuated tritone mask hereafter referred to as att-PSM. The masks are employed in a double exposure method in which the alt-PSM with FSSB is used to primarily define a shrunken gate structure in a first exposure. The scattering bars enable a smaller phase width as illustrated in FIG. 6b that effectively permit a smaller gate size to be controllably manufactured. Phase height and phase width can be adjusted to improve depth of focus, especially for relaxed pitches and isolated lines. The optical proximity effect (OPE) is reduced by introducing the FSSB and this allows a higher flexibility in mask design. In addition, the effect of lens aberrations such as x-coma is minimized with the new alt-PSM which results in higher fidelity photoresist features, especially those with dimensions below the half wavelength size.
The chrome section of the tritone att-PSM protects the gate feature defined with the alt-PSM by preventing the erasure of phase shifting regions and preventing the creation of undesirable artifact regions that would otherwise be formed by the alt-PSM exposure. The scattering bar feature which is combined with the attenuated portion in the tritone att-PSM trims the polysilicon interconnect line to a smaller dimension than can be achieved with a binary mask. This enables the polysilicon interconnect to be shrunk at the same time as the gate feature. The blocking area (chrome region) of the att-PSM is based on the phase assignment of the alt-PSM. Examples of the alt-PSM with FSSB and the tritone att-PSM are found in FIGS. 3a and 3b, respectively.
A comprehensive data management flow is crucial to building quality masks for this double exposure approach. The system for producing phase shifting data is a command script comprised of alt-PSM design rules, OPC, scattering bar rules, and gate blocking area generation for the tritone att-PSM. The management flow involves first reading in the layout of diffusion (underlying active area) and poly layers. Next, design of the alt-PSM mask follows a sequence of alt-PSM rule check, assigning FSSB for small linewidths, assigning phases along gate area, and inputting OPC data. The next step is inputting the blocking area for shrunken gates including the assigned phase areas and polygate areas. Then the trim mask is designed by inserting data for polysilicon interconnects, the block area, and full size scattering bars that is generated through a set of parameters such as scattering bar size and separation between main pattern and scattering bar. After OPC data is determined and corrections are inputted, the final output is a modified GDS layout for the each mask. The GDS layout is subsequently used by the mask fabricators to produce the masks.